1. Field of the Invention
Generally, the present disclosure relates to the formation of integrated circuits, and, more particularly, to the formation of high performance transistors having a low contact resistance, possibly in combination with strain control mechanisms to adjust the strain in the channel region for enhancing charge carrier mobility in the channel region of a MOS transistor.
2. Description of the Related Art
Integrated circuits typically include a very large number of circuit elements, such as transistors, capacitors, resistors and the like, which are formed on the basis of an appropriate semiconductor material that is provided above a suitable substrate. In modern ultra-high density integrated circuits, device features are steadily decreasing to enhance device performance and functionality. Shrinking the feature sizes, however, entails certain problems that may partially offset the advantages obtained by the reduced feature sizes. Generally, reducing the feature sizes of, for example, a field effect transistor element, may lead to a decreased channel resistance for a given transistor width in the transistor element and thus result in a higher drive current capability and enhanced switching speed of the transistor. In decreasing the features sizes of these transistor elements, however, the increasing electrical resistance of conductive lines, such as the gate electrodes or other polysilicon lines and contact regions, i.e., of regions that connect transistor areas, such as drain and source regions, with the periphery of the transistor element becomes a dominant issue, since the cross-sectional area of these lines and regions also decreases with decreasing feature sizes. The cross-sectional area, however, determines, in combination with the characteristics of the material comprising the conductive lines and contact regions, the resistance thereof.
The above problems may be exemplified for a typical critical feature size in this respect, also referred to as a critical dimension (CD), such as the length of the channel of a field effect transistor that forms below a gate electrode between a source region and a drain region of the transistor. Reducing the channel length may significantly improve device performance with respect to fall and rise times when operating the transistor element in a switched mode due to the reduced capacitance between the gate electrode and the channel and due to the decreased resistance of the shorter channel. Shrinking the channel length, however, also entails the reduction in size of any conductive lines, such as the gate electrode of the field effect transistor, which is commonly formed of polysilicon, and the contact regions that allow electrical contact to the drain and source regions of the transistor. Consequently, the available cross-section for charge carrier transportation is reduced. The conductive lines and contact regions may therefore exhibit a higher resistance unless the reduced cross-section is compensated for by improving the electrical characteristics of the material forming the lines and contact regions, such as the gate electrode and the drain and source contact regions.
It is thus of particular importance to improve the characteristics of conductive regions that are substantially comprised of semiconductor material, such as silicon. For instance, in modern integrated circuits, the individual semiconductor devices, such as field effect transistors, capacitors and the like, are currently and will be in the foreseeable future primarily based on silicon, wherein the individual devices are connected by silicon lines and metal lines. While the resistivity of the metal lines may be improved using highly conductive metals, such as, copper, tungsten, silver, metal alloys and the like, process engineers are confronted with a challenging task when an improvement in the electrical characteristics of silicon-containing semiconductor lines and semiconductor contact regions is required. Thus, a highly conductive metal silicide is typically formed in polysilicon lines, such as gate electrodes and the drain and source regions, since the metal silicide typically exhibits a significantly higher conductivity compared to polysilicon and crystalline silicon even when highly doped. In conventional techniques, a plurality of highly sophisticated silicidation schemes are employed in order to provide the desired electrical characteristics. For example, refractory metals, such as nickel, platinum, cobalt, titanium, tungsten and the like, or combinations thereof, may be used for increasing the conductivity of polysilicon lines and contact regions. Irrespective of the specific silicidation regime used, the process is typically performed after completing the transistor devices and prior to forming the interlayer dielectric material, i.e., after performing any high temperature anneal processes for activating dopants in the drain and source regions and reducing implantation-induced lattice damage, since the conductive metal silicide materials are typically unstable at elevated temperatures as required for the dopant activation. Thereafter, respective contact plugs are formed in the interlayer dielectric material to provide electrical contact to the respective circuit regions, such as drain and source regions, gate electrodes, capacitor electrodes and the like, wherein the resulting contact resistance may be moderately low due to the provision of the metal silicide.
Generally, a plurality of process technologies are currently practiced, wherein, for complex circuitry, such as microprocessors, storage chips and the like, CMOS technology is currently one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using CMOS technology, millions of transistors, i.e., N-channel transistors and P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A field effect transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, comprises so-called PN junctions that are formed by an interface of highly doped drain and source regions with an inversely doped channel region disposed between the drain region and the source region.
The conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed near the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on the dopant concentration, the mobility of the majority charge carriers, and, for a given extension of the channel region in the transistor width direction, on the distance between the source and drain regions, which is also referred to as channel length.
Thus, one efficient mechanism for increasing the transistor performance includes increasing the charge carrier mobility by modifying the lattice structure in the channel region, for instance by creating tensile or compressive stress in the vicinity of the channel region to produce a corresponding strain in the channel region, which results in a modified mobility for electrons and holes, respectively. For example, compressive strain in the channel region for a standard silicon layer may increase the mobility of holes, thereby providing the potential for enhancing the performance of P-type transistors. On the other hand, the creation of tensile strain in the channel region of an N-channel transistor may increase electron mobility. Consequently, a plurality of strain-inducing mechanisms may be used, such as strained or relaxed semiconductor material within a silicon base material in order to provide a desired type and magnitude of strain in the channel region. In other cases, stressed material layers, such as overlying dielectric materials, spacer elements and the like, may be provided, possibly in combination with strained or relaxed semiconductor materials, to obtain an even increased strain effect in the channel region. Other strain-inducing sources may also contribute to the finally achieved transistor performance, such as stressed isolation structures and the like. Also, the metal silicide regions, formed on gate electrodes and drain and source regions, may have a significant influence on the total strain created in the respective channel region. For example, typically used metal silicide materials, such as cobalt silicide and nickel silicide, exhibit a substantial tensile stress, which may negatively affect the strain-inducing mechanism provided by, for instance, an embedded silicon/germanium material, compressively stressed liners and the like. Consequently, the overall performance gain of the transistor that is expected due to the employment of sophisticated strain sources may be reduced.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.